1. Field of Invention
The present invention relates to a semiconductor structure, and more generally to a test pattern structure.
2. Description of Related Art
Generally, a semiconductor device is fabricated by performing a series of processes including deposition processes, photolithography processes, etching processes, and ion implantation processes. Upon completion of one or more of the above-mentioned processes, defects such as particles, misalignments, over-etching or under-etching may be generated in the semiconductor device. Therefore, various test pattern structures are designed in the scribe line region for testing the performance of the semiconductor devices in the chip or monitoring defect existence and distribution within the wafer.
Rc (contact resistance) of a contact or via is an index for the interconnection performance. FIG. 1 schematically illustrates a conventional test pattern structure in a cross-sectional view. Referring to FIG. 1, a metal line 12, via plugs 14 and another metal line 16 are sequentially disposed on a substrate 10. The metal line 12, the via plugs 14 and the metal line 16 are connected to form a serpentine structure. Either discontinuity within the serpentine structure or poor interface between the metal line and the via plug would render the measured resistance high. However, when high Rc of via occurs, it is difficult to identify that the failure interface is between the metal line 12 and the via plugs 14 (connection interface A) or between the via plugs 14 and the metal line 16 (connection interface B), unless a time-consuming cross-section SEM is implemented. Moreover, since the cross-section SEM is usually conducted at a single point, the mapping of failure interfaces through the wafer is unlikely to be obtained.
Accordingly, a test pattern structure which can identify the failure interface in the interconnection structure quickly and correctly without performing a cross-section SEM is deeply desired in the industry.